Design and evaluation of 6T SRAM layout designs at modern nanoscale CMOS processes

Six layout variations of the 6T SRAM cell are examined and compared. The comparison includes four conventional cells, plus the thin cell commonly used in industry and a recently proposed ultra-thin cell. The layouts of the cells are presented and corresponding memory arrays are implemented at 65, 45 and 32 nm using 3-metal CMOS n-well process. The obtained designs are compared in terms of area, power dissipation and read/write delay, using proper BSIM4 level simulations. The thin cell presents the best results regarding area efficiency and delay. In terms of power dissipation, it performs poorly at 65 and 45 nm but appears to be the best at 32 nm, presenting great improvement with downscaling. The ultrathin cell provides a more lithographically friendly alternative to the thin cell, with lower power dissipation at 65 and 45 nm and higher at 32 nm. Overall, it performs worse in area and power relative to most conventional designs and gets worse with downscaling. Keywords—SRAM; layout; 6T cell; memory array; delay; power;